1. Field of the Invention
This invention relates to a semiconductor sensor, and more particularly to a field-effect transistor-type sensor used for detecting the constituents of a solution.
2. Description of the Prior Art
In general, an ion-sensitive field-effect transistor (hereinafter, simply referred to as an ISFET) is known as an FET-type chemical sensor that detects the constituents of a solution. An ISFET comprises a source region and a drain region formed on a semiconductor substrate, and a gate portion having a gate-insulating film and a film sensitive to a specific ion of a solution. When the gate portion of the ISFET is immersed in a solution, the conductance between the source and drain regions changes in proportion to the ion concentration of specific constituents of the solution.
The ISFET detects the changes of such conductance and produces output signals corresponding to the ion concentration. Specifically, interface potentials are generated on the surface of the ion-sensitive film by the effect of a specific ion of the solution. Such interface potentials cause the conductance between the source and drain regions to change. This can be performed through the gate-insulating film.
As described above, at least the gate portion of an ISFET is immersed in a solution while in use. Thus, the ISFET must be protected from the penetration of the solution. Therefore, various configurations of electrical insulation have been considered to protect the electrodes and leads from deteriorating. For example, an ISFET that can securely protect its electrodes was disclosed by the inventor of the present invention.
FIG. 11 shows the configuration of the disclosed ISFET which employs a direct bonding-type semiconductor substrate. In FIG. 11, a first silicon substrate 41 and a second silicon substrate 42 are directly bonded to each other interposing an oxide film 43 therebetween. Such a direct-bonding configuration can be obtained in such a manner as follows. First, the surfaces of substrates to be bonded are polished to achieve a mirror finish. Next, a silicon oxide film is formed on at least one of the surfaces, and then the surfaces are cleaned. Thereafter, the surfaces of substrates are contacted to each other, and then are exposed to an atmosphere of a prescribed thermal processing. The first substrate 41 of the thus bonded substrates is etched by the use of a selective etching technique so as to form an island-shaped substrate. A source region 44 and a drain region 45 are formed in the island substrate 41. A P.sup.- -type channel region 46 is formed near the interface between the first and second substrates 41 and 42. A P.sup.+ -type channel stopper layer 47 is formed adjoining the P.sup.- -type channel region 46.
The second substrate 42 is selectively etched so as to form an opening 48 at a position opposite to the channel region 46. Further, the bonded side of the first substrate 41 is partially exposed to the opening 48. A gate-insulating film 49 of silicon oxide and an ion-sensitive film 50 of silicon nitride are deposited on the exposed portion of the first substrate 41 and the walls of the opening 48. These constitute an ion-sensitive portion 51. The surfaces of bonded substates 41 and 42 are also coated with such films 49 and 50 for the purpose of water-resistance. The source and drain electrodes 52 and 53 are formed on the surface of the first silicon substrate 41, respectively. However, the ion-sensitive film 50 of silicon nitride is not required on the side in proximity of the electrodes 52 and 53. Thus, other materials may also be used for water-resistance.
In this configuration, the ion-sensitive portion 51 is formed on one side of the first substrate 41, while the source and drain electrodes 52 and 53 are formed on the other side of the substrate 41. Thus, the electrodes 52 and 53 are not immersed in a solution, but only the sensitive portion 51 of the ISFET is immersed therein. Therefore, the ISFET is free from deterioration in terms of insulation characteristics caused by the penetration of a solution. Further, the ISFET can be manufactured by the use of planar processes.
However, the above-described ISFET still has many disadvantages including the following. Specifically, as shown in FIG. 11, the sensitive portion 51 is formed in a concave portion of the ISFET. Thus, the uniform thickness of the films 49 and 50 cannot be manufactured with consistent accuracy. Further, the ISFET is usually attached to a tube, and a solution to be measured flows through the tube. In this case, the concave portion 51 (i.e., the ion-sensitive portion) is immersed in the solution as described above. Thus, the solution can stagnate in the concave portion 51. Such stagnation prevents the efficient replacement of the solution with a fresh supply for subsequent measurement.
On the other hand, a technique for eliminating the above-described disadvantages has been disclosed. Specifically, according to such a technique, an ion-sensitive portion is not provided in a concave portion of the substrate, but in an island portion thereof. This means that the solution does not contact the concave portion, resulting in no stagnation of the solution. A uniform thickness of the ion-sensitive film and the gate-insulating film may also be formed. However, it is extremely difficult to embody an ISFET on the basis of such a technique because of the following reasons. In the technique, a thin film of silicon, which comprises the island portion, is formed on a quartz substrate. Source and drain regions are formed within the island portion. An ion-sensitive film is formed on the surface of the island portion through a gate-insulating film. Thus, two openings and two through holes must be made in the quartz substrate so as to form source and drain electrodes. However, it is extremely difficult to make holes in the quartz substrate which has strong corrosion resistance. It is theoretically possible to make holes in the quartz substrate if an etching process using hydrogen fluoride is performed for a long time of about 20 hours. Practically, masking materials, which can withstand such a long-time etching, are very hard to obtain. Above all, making a hole deeper as compared to an opening area involves great difficulties in terms of anisotropic etching.
Moreover, the disclosed technique claims that a monocrystalline silicon layer of 0.5 to 1 .mu.m thick is formed on the quartz substrate. However, at present, forming a monocrystalline silicon layer on quartz, per se, is extremely difficult, and no experimental results on such formation have been located. Even if such a monocrystalline silicon layer is formed on a quartz substrate, the layer is only 0.5 to 1 .mu.m thick. Thus, such a thin silicon layer can easily cause mechanical damage or undergo a peel-off phenomenon. In addition, quartz differs significantly from monocrystalline silicon in coefficient of thermal expansion. As a result, the thin monocrystalline silicon layer is subjected to higher stresses causing the layer to peel off.